Processor-based systems rely on different kinds of memory devices for data storage. Memory devices include non-volatile kinds, such as read-only memory (ROM), hard disk drives and compact disk (CD) ROM drives, as well as volatile media, known as random access memory (RAM). The RAM is directly accessible by the processor, so data stored on the hard disk drive is loaded into RAM before processing can begin.
A processor-based system, such as a personal computer, may include more than one type of RAM. One such memory is static RAM (SRAM), which stores data in a flip-flop. Because SRAM cells need not be refreshed, they operate at faster speeds than one-transistor dynamic RAM (DRAM) cells. SRAM cells are typically used for level-one and level-two caches within the processor-based system.
High-performance very large scale integration (VLSI) systems employ large amounts of on-die SRAM for the cache function. As scaling of such technologies continues, particular attention is given to the performance of the SRAM as well as its die size. Since the SRAM cell supports both read and write operations, its performance is measured by its read stability and its write margin. “Read stability” may be loosely defined as the probability that during a read operation performed upon a cell, the cell will “flip” its content. Write margin may be loosely defined as how low the bit-line voltage level must be to flip the cell, i.e., to accomplish a successful write.
The read stability and the write margin make conflicting demands on the SRAM cell. During a read operation, the SRAM cell preferably has “weak disturbance” at the internal storage nodes in order to avoid being erroneously flipped (from a “1” state to a “0” state, and vice-versa). This is the preference whether a “true read,” in which the contents of the cell are sent to read/write circuitry, or a so-called “dummy read,” in which the read is not actually processed, takes place. During a write operation, the SRAM cell preferably has “strong disturbance” in order to successfully flip the cell. Thus, read stability depends on weak disturbance within the SRAM cell while write margin depends on strong disturbance within the same SRAM cell.
For the current generation of SRAM memory, cell scaling is limited by both the read and write operations. Thus, there is a continuing need to design an SRAM memory cell that meets both the read stability and the write margin requirements, while a minimum cell area is maintained.